Superconducting Platform Technologies

Expected Outcome

This action will consolidate Europe’s position in superconducting quantum computing through:

• Establishment of a full-stack superconducting quantum computer aiming at 1.000 physical qubits and QPU architecture based on chiplet technology. The system should feature a scalable and user-adjustable architecture, T1 coherence time above 100 us, gate fidelities (both one- and two-qubit gates, and read-out) of at least 99.9%, read-out speed below 300 ns, two-qubit gate speed below 20 ns.
• Demonstration of quantum advantage on selected industrial use cases, validated through benchmarking with best-in-class classical methods.
• Deployment of a cloud-accessible quantum system integrated with high-performance computing environments.
• Maturation of fault-tolerant quantum computing protocols, including effective quantum error correction and noise mitigation schemes.
• Delivery of a comprehensive, standardised software stack supporting system bring-up, calibration, control, benchmarking, and user access.

Strengthened supply chains and industrial capacity in Europe for superconducting quantum technologies.

Scope

The proposal should contribute to the scale-up and practical deployment of superconducting quantum computing platforms and must address at least two of the critical technical roadblocks identified in the SRIA 2030, among which necessarily:

1. Error Correction and Fault Tolerance: the implementation of error correction and fault-tolerant quantum computing via significant improvements in gate fidelity, coherence times, and noise mitigation strategies.
2. Cryogenic and Interconnect Engineering: integration with cryoelectronic and efficient signal routing at low temperatures at the scale of 1,000+ qubits, also addressing the scalability issues that prevent the implementation of an industrial-grade quantum computing platform

In addition, the proposal should address the following:

• Construction and demonstration of a modular superconducting quantum computer with high-fidelity gates and scalable architecture.
• Integration of all required layers: quantum hardware, cryogenic infrastructure, control electronics, and a full-stack software suite.
• Establishment of mature test and measurement capabilities at the production sites, in particular cryogenic screening capacity of chiplets for the early identification of perfectly working chiplets before being assembled in the final QPU package.
• Establishment of full interoperability and open standards across the various chiplet manufacturers. The project should also pursue the development of standards and EU-wide certification schemes.
• Development and validation of advanced error correction and fault-tolerance schemes suited for superconducting qubits.
• Demonstration of real-life use cases (minimum of two) addressing relevant industrial challenges within the lifetime of the project. Use cases should show quantum advantage or clear progression towards it, with validation against classical methods.
• Deployment of a full software stack to operate the system, including tools for calibration, control, performance verification, benchmarking, and interfacing with classical computing environments.
• Development of standardised interfaces and APIs for access, control, and hybrid workflows, ensuring interoperability with classical HPC systems and cloud-based platforms.
• Provision of remote access capabilities to enable wide use by academic, research, and industrial communities across Europe.
• Contribution to the creation of a robust and independent European supply chain for superconducting quantum technologies, including scalable cryogenics, high-fidelity readout and control electronics, and superconducting chip fabrication.
• Open access to the system for co-design and evaluation of algorithms, supported by training resources and documentation.

Technology Readiness Level - Technology readiness level expected from completed projects

The rules are described in General Annex B of the Horizon Europe Work Programme 2026-2027.

Activities are expected to start at TRL 4 and to achieve TRL 7 by the end of the project