Large-Scale Photonic Quantum Computing Platform Technologies

Expected Outcome

This action will establish a strategic European initiative to develop scalable, modular, and interoperable photonic quantum computing platforms. Proposals for this topic are expected to address and provide credible solutions to at least two major technical roadblocks currently limiting the advancement of photonic quantum computing such as:

• The lack of deterministic, high-efficiency photonic entanglement and loss-tolerant architectures suitable for fault-tolerant scaling
• The absence of a standardised, integrated control stack combining photonic hardware, firmware, and system software with reliable benchmarking across platforms

Project results are expected to contribute to the following expected outcomes:

• By 2028, demonstration of a photonic NISQ processor with ≥100 photonic qubits, integrating deterministic single-photon sources, low-loss waveguides, on-chip detectors, and a firmware stack (scheduler, controller, compiler), validated via hardware-agnostic benchmarks and hybrid photonic-HPC applications demonstrating classical-quantum crossover
• By 2030, delivery of a full-stack, high-connectivity photonic quantum computer, with modular scalability, integrated on-chip and fibre-based interconnects, and high-fidelity gates (e.g. error rates ≤10⁻³) with an indicative target of 1 000 photonic qubits, laying the groundwork for prototype demonstrations of quantum utility on industrially relevant workloads.
• System-level interoperability and standardisation, with published interface specifications across photonic quantum hardware and software stacks including packaging, APIs, compiler interfaces, and cloud protocols compatible with telecom wavelengths
• Validation of entanglement distribution across modules through standardised protocols and field-demonstration of interconnected photonic quantum processors
• Acceleration of industrialisation and commercialisation, including a roadmap for pilot manufacturing lines, quality assurance protocols, and development of a sovereign European supply chain for photonic quantum technologies
• Demonstration of project results through a concrete use case provided by a major end-user partner within the consortium, validating the platform’s relevance and performance under real operational constraints.

Scope

Proposals for this topic are expected to be led by a startup with demonstrated expertise in photonic quantum computing. The startup should collaborate with relevant academic, industrial, and RTO partners to ensure both technological depth and market orientation. The consortium should also include at least one major end-user whose operational needs will shape the platform design, and whose infrastructure will host the field demonstration of the project’s results.

Proposals should implement a coordinated, durable R&I programme that integrates hardware, software, system architecture, and application-level use cases. Activities should include:

• Platform development advancing open, scalable photonic quantum processors with semiconductor and/or glass-based photonic chips, integrated control electronics, firmware, and robust error mitigation and correction schemes
• System integration realising modular quantum nodes with photonic interconnects and validating scalable architectures under realistic noise, loss, and control constraints
• Software stack co-design integrating low-level firmware, compilers, hybrid algorithms, and network APIs to demonstrate application-level quantum advantage and HPC interoperability

Proposals are expected to build upon prior Quantum Flagship results and demonstrate capacity to contribute actively to the governance and strategic coordination of the EU quantum computing ecosystem, including synergies with STEP, Chips JU, IPCEI projects and EuroHPC.

Technology Readiness Level - Technology readiness level expected from completed projects

Activities are expected to start at TRL 4 and achieve TRL 7 by the end of the project - see General Annex B.